1. Field of the Invention
The present invention relates to a self-synchronizing descrambler comprising n clocked shift register stages for descrambling a signal having a scrambler period of 2.sup.n -1 bits, whereby the output of at least one shift register stage is connected to the input of at least one modulo-2 adder.
2. Description of the Prior Art
Pulse patterns having a disturbing DC component or a particularly high energy component at other, discrete frequencies can occur in digital signal transmission insofar as involved recodings are not undertaken. In order to avoid these patterns, the digital signal to be transmitted is scrambled at the transmitting side by a modulo-2 addition with a pseudo-random sequence. The descrambling occurs at the receiving side by a further modulo-2 addition with the pseudo-random sequence employed at the transmitting side. The synchronization of the pseudo-random generators employed at the transmitting and receiving side which is thereby necessary can be avoided by employing free-wheeling and, therefore, self-synchronizing scrambler and descrambler arrangements.
With the further expansion of the digital telecommunications system, the necessity of constructing the scrambler arrangement and the descrambler arrangement for digital signals having the high transmission rate arises.
"Siemens Forschungs-und Entwicklungsberichte", Vol. 6, No. 1, 1977, pp. 1-5, fully incorporated herein by this reference, discloses a possibility for constructing scrambler and descrambler arrangements for pulse code modulated (PCM) signals having a high clock frequency. The PCM signals are thereby scrambled in a plurality of parallel channels having a comparatively lower bit repetition frequency and the scrambled signals are combined to form the transmission signal by multiplexing. The demultiplexer is analogously provided at the receiving side, the parallel descrambling in a plurality of channels having a low bit repetition frequency following thereat. In addition to the high expense, the necessity of synchronizing multiplexers and demultiplexers with one another occurs in such a solution.